1. Field of the Invention
The present invention relates to a carrier synchronizing circuit and a carrier synchronizing method, and particularly to a carrier synchronizing circuit and a carrier synchronizing method that can quickly and stably establish synchronism with a carrier without degrading transmission quality even when a frequency drift in a local oscillator is large and even when the frequency detection accuracy of a frequency synchronizing unit is not very high.
2. Description of the Related Art
Recently remarkable progress has been made in wireless digital transmission technology including communication for portable telephones, satellite wave or terrestrial wave digital broadcasting, wireless LAN (Local Area Network) communication and the like. In a wireless digital signal transmission system, establishment and acquisition of stable synchronism with a carrier is very important for high transmission quality.
For establishment of synchronism, it is necessary to accurately detect a frequency difference between local oscillation frequency of a receiver (frequency of a local oscillator) and frequency of a carrier, that is, a frequency error Δf of the local oscillator as well as a phase deviation θ caused by a transmission line, an RF (Radio Frequency) circuit of a sender and a receiver, and the like, and control the frequency and phase of a received signal in such a manner as to cancel each of the frequency error Δf and the phase deviation θ.
Although a PLL (Phase-Locked Loop) is often used as a typical example of a carrier synchronizing method, a range of frequency errors that can be cancelled by the PLL (capture range) is not very wide. Therefore, when a frequency error exceeds the capture range, another carrier synchronizing method having a wider capture range needs to be applied.
However, a trade-off relation generally holds such that when the capture range becomes wider, frequency error detection accuracy is roughened. Therefore, a method is often used which first roughly pulls in frequency to a frequency error in a certain range (that is, achieves frequency synchronism) by a synchronizing method having a wide capture range and then achieves final carrier synchronism (phase synchronism) including a phase component by a high-precision synchronizing method of a PLL or the like (see for example Japanese Patent Laid-Open No. Hei 10-126455, and Japanese Patent Laid-Open No. 2002-111768).
FIG. 1 is a block diagram showing an example of an existing carrier synchronizing circuit.
A carrier synchronizing circuit 1 includes a frequency synchronizing unit 2, a low-pass filter (LPF) 3, and a phase synchronizing unit 4. In this carrier synchronizing circuit 1, the frequency synchronizing unit 2 pulls in an input received signal to a frequency in a predetermined range. The low-pass filter 3 then removes a high-frequency component, thereby suppressing thermal noise outside a modulation band and interference of an adjacent channel or the like. The phase synchronizing unit 4 performs high-precision phase pull-in by a PLL or the like, whereby carrier synchronism is established.
The frequency synchronizing unit 2 and the phase synchronizing unit 4 will be described in more detail.
The frequency synchronizing unit 2 includes a frequency error detector (FD) 11, a numerically controlled oscillator (NCO) 12, and a multiplier 13.
The frequency error detector 11 is supplied with a signal after filter processing from the low-pass filter 3. The frequency error detector 11 detects a frequency error Δf from the signal after the filter processing, and then outputs the frequency error Δf to the numerically controlled oscillator 12. A method is described in Non-Patent Document, U. Mengali and A. N. D' Andrea, Synchronization Techniques for Digital Receivers, Plenum Pub Corp Published 1997/11, “Chapter 3” for example. The method above or the like can be used as a method for detecting the frequency error Δf in the frequency error detector 11. The numerically controlled oscillator 12 generates a phase rotator ej2πΔft (the signal of the phase rotator ej2πΔft) having the frequency error Δf from the frequency error detector 11 as a period, and then outputs the phase rotator ej2πΔft (the signal of the phase rotator ej2πΔft) to the multiplier 13.
The multiplier 13 multiplies the received signal input to the frequency synchronizing unit 2 by a complex conjugate (the signal of the complex conjugate) of the phase rotator ej2πΔft output from the numerically controlled oscillator 12.
Thus, in the frequency synchronizing unit 2, the frequency error Δf of the signal obtained by subjecting the received signal after frequency synchronizing processing to the filter processing is detected, and the phase rotator ej2πΔft having the frequency error Δf as a period is generated. Then, the complex conjugate of the generated phase rotator ej2πΔft is multiplied by the received signal, whereby phase rotation of the received signal which phase rotation is caused by the frequency error Δf is cancelled out.
The phase synchronizing unit 4 includes a phase error detector (PD) 21, a loop filter 22, a numerically controlled oscillator (NCO) 23, and a multiplier 24.
The phase error detector 21 detects a phase error of a signal output by the multiplier 24, and then outputs the phase error to the loop filter 22. In this case, letting Δf′ be a frequency error remaining after the frequency synchronizing processing in the frequency synchronizing unit 2, and letting θ be phase deviation occurring in a transmission line, an RF circuit of a sender and a receiver, and the like, the phase error detected by the phase error detector 21 can be expressed as (2πΔf′t+θ).
The loop filter 22 is an IIR (Infinite Impulse Response) type loop filter. The loop filter 22 averages the phase error (2πΔf′t+θ) output by the phase error detector 21, and then outputs the result to the numerically controlled oscillator 23.
More specifically, the loop filter 22 includes multipliers 31 and 32, an integrator 33, a delay element 34, and an adder 35. First, the multiplier 31 or 32 multiplies the phase error (2πΔf′t+θ) (the signal of the phase error (2πΔf′t+θ)) output from the phase error detector 21 by g1 or g2, respectively. That is, the multiplier 31 or 32 is a weighting multiplier that adds the weight of the coefficient g1 or g2, respectively, to the input signal.
The integrator 33 adds the phase error (2πΔf′t+θ) multiplied by g2, which phase error is the output of the multiplier 32, to an output of the integrator 33 which output precedes by one symbol period and is an output of the delay element 34. The integrator 33 then outputs the result to the delay element 34 and the adder 35. The delay element 34 delays (retains) the output from the integrator 33 by one symbol period, and then outputs the delayed output to the integrator 33. The adder 35 adds the output of the multiplier 31 to the output of the integrator 33, and then outputs the result to the numerically controlled oscillator 23.
The numerically controlled oscillator 23 generates a phase rotator ej(2πΔf′t+θ) of a phase quantity corresponding to the phase error (2πΔf′t+θ) output by the loop filter 22, and then outputs the phase rotator ej(2πΔf′t+θ) to the multiplier 24. The multiplier 24 multiplies the received signal after the filter processing which signal is output by the low-pass filter 3 by a complex conjugate (the signal of the complex conjugate) of the phase rotator ej(2πΔf′t+θ) output from the numerically controlled oscillator 23.
Thus, in the phase synchronizing unit 4, the phase error (2πΔf′t+θ) of the signal obtained by subjecting the received signal after the frequency synchronizing processing to the filter processing is detected and averaged. Then, the complex conjugate (the signal of the complex conjugate) of the phase error (2πΔf′t+θ) after the averaging is multiplied by the received signal output from the low-pass filter 3, whereby the phase error (2πΔf′t+θ) included in the received signal is cancelled out.
By using the carrier synchronizing circuit including the frequency synchronizing unit and the phase synchronizing unit independently as described above, it is possible to establish carrier synchronism with reliability and high precision even when there is a relatively large frequency error.